Flexible iterative receiver architecture for wireless sensor networks: a joint source and channel coding design example

Due to their computational complexity, iterative decoder components such as source and channel decoders are usually implemented using specialized dedicated hardware. This leads to the scenario where each different iterative decoder component of the receiver requires its own hardware. Owing to their relatively high complexity, many capacity-approaching techniques proposed in the literature have not yet been invoked in Wireless Sensor Network (WSN) applications, despite their potential benefits of facilitating a reduced transmission power or extended communication range. Against this background, we propose an energy-efficient architecture comprised of multiple Computation Units (CUs), which is sufficiently flexible for accommodating different iterative decoder components using the same hardware. In this work, the flexible architecture is applied to Joint Source and Channel Coding (JSCC), comprising the Unary Error Correction (UEC) code, a turbo code, and an iterative demodulator. We conceive a flexible technique for controlling the hardware, which supports a high hardwareexploitation ratio for the CUs, reaching a utilization of 88%, compared to 68% achieved in similar solutions reported in the open literature.